This invention relates to programmable logic, and in particular to an active driver circuit particularly suited for a high speed programmable logic device.
A programmable logic device (PLD) is a programmable integrated circuit that allows the user of the circuit, using software control, to customize the logic functions the circuit will perform. A typical PLD consists of an array of identical logic cells that can be individually programmed, and which can be arbitrarily interconnected to each other to provide internal input and output signals, thus permitting the performance of highly complex combinational and sequential logic functions. The program is implemented in the PLD by setting the states of programmable elements such as memory cells.
One type of programmable logic, known as programmable logic arrays (PLA), is a combinatorial two-level AND/OR integrated circuit which can be programmed to perform sum-of-products logic. Such devices typically consist of a series of AND gates having input terminals which can be programmably connected to chip input signals, and a series of OR gates which may be programmably connected to receive the output signals from the AND gates.
Another type of programmable logic device is known as programmable array logic (PAL). PALs use a fixed OR array and bidirectional input/output pins. A disadvantage of both PALs and PLAs is the lack of density with which they may be programmed. In other words, although the array is capable of performing many logic functions, utilization of the array is not as complete as desirable. Furthermore the size of the array increases faster than its programming capability.
A response to this problem has led to the development of the field programmable gate arrays (FPGAs) which have "macrocells" or logic blocks in programmable logic devices. A macrocell or logic block is a small grouping of logic capable of performing many different functions, and being selectively interconnectable to other macrocells or logic blocks. This allows the logic in the programmable logic device to assume a more granular structure in which pieces of the logic communicate with other pieces, to provide an overall more efficient utilization of the integrated circuit. For purposes of the present specification, "programmable logic device" is defined as a programmable array logic (PALs), programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), and other types of programmable logic devices (PLDs).
A significant disadvantage of all programmable logic devices presently available is their relatively slow speed. In all of the programmable logic devices described above, the connections within the AND and OR arrays, as well as to and from the macrocells, are made by various transfer gates. Examples of transfer gates include erasable programmable read only memory cells, electrically erasable read only memory cells, static random access memory cells, fuses, antifuses, or the like. In each of these cases, the interconnection approach is passive. That is, the state of the transfer gate is itself used to control some other apparatus which makes or breaks a connection between two nodes, and the signals presented to the connection simply pass through the connection (or do not pass if the connection is open). As a result, the overall speed of the programmable logic device is limited. One of the primary reasons for the relatively slow operating speed of prior art programmable logic devices is the resistance present in the interconnection system. The interconnection system is the programmable "wiring" by which the logic signals are propagated across the integrated circuit chip. This propagation speed is limited by the series resistance of the transfer gates employed, whether formed as EPROM cells, SRAM cells, antifuses, or otherwise.
To overcome these drawbacks, the aforementioned passive interconnection system is replaced by an active interconnection system such as the system described in U.S. Pat. No. 5,504,440 to Sasaki, which is assigned to the assignee of the present invention. Disclosed therein is an architecture for a programmable logic device that includes controllable active buffer circuits to interconnect the programmable logic elements, as well as input and output data buses. In this fashion, the programmable logic device operates at substantially faster clock rates than programmable logic devices employing passive interconnect circuitry.
U.S. Pat. No. 5,614,844 to Sasaki et al., which is assigned to the assignee of the present invention, discloses active device drivers for programmable logic devices. The active device drivers are described as formed from BiCMOS technology. In this fashion, the speed advantages of bipolar technology is achieved while taking advantage of the lower power consumption of CMOS technology.
What is needed, however, is an active driver circuit for a programmable logic device which consumes less power than the prior art without unduly reducing the operating speed of a programmable logic device.